New core, possibility to bypass PCIE traffic limitation?

[ProDigit]

Is it possible to program future cores to bypass the PCIE bandwidth bottleneck on PCIE 1x slots using faster graphics cards?
If it was possible to send data more continuous, and buffer in VRAM, vs short peaks or bursts of data that are throttled by the PCIE 1x speed...

PCIE 5.0 is on the horizon, but the majority of the hardware will still have at least a few PCIE 1x slots; that seem to perform quite poorly under Windows.

[Joe_H]

Probably not. The reason is that a GPU is not a general purpose processor like a CPU, for the calculations being done it is essentially being used as an attached vector processor for the data contained in the WU. Essentially a block of data is passed to the GPU with a specific set of operations to be performed on it. Each block then has to be coordinated with the adjacent blocks. After a pass through all of the data the results become the inputs for the next pass. I don;t really see an opportunity to buffer any of that data.

At no time is all of the WU data sent to the GPU, for larger WU's it might not fit on the largest cards anyways. On top of that, VRAM is holding the output from the shaders in a video format, I don't think the shaders can read from it.

[JimboPalmer]

Just to be clear, this Forum is for CPU projects, and CPU projects do not have PCIE issues.

Edit by Mod: Topic Moved to correct that issue.
Thanks for noticing.