Folding Forum

Touchee

John thanks, I really was under the impression the port was made impossible due to (among others?) the reason I said above, so thanks for the correction!

And I think everyone is waiting for SMP2

MtM wrote:@yashbudini it's not only relevant how high the utilisation of each core is, it's also very relevant to how balanced the execution of each thread is in regards to the others. This is also the main argument toTow focuses on with his view on the current linux 2.10 core issues. If one thread has to wait for the others it slows down the computing process, so while in theory a tri core could offer the same performance for each thread as a quad core ( assuming about 75% usage on the quad which isn't exactly true but let's use it for arguments sake ) the synchronisation between the threads would negatively impact the final performance.

Looking at it from a slightly different perspective if xxx WU with 4 threads could be changed to 5 smaller threads could the end result still come out in your (and mine) favor?

YashBudini wrote:Looking at it from a slightly different perspective if xxx WU with 4 threads could be changed to 5 smaller threads could the end result still come out in your (and mine) favor?

There is no general yes or no answer to this type of question.

First, read ihaque's explanation HERE. He's talking about parallelism in GPUs, but a lot of what he says also applies to SMP.

If you have 5 completely independent tasks and only four workers and the total processing time is the same as four completely independent tasks, then the only differences will depend on how effectively your OS shares resources when it is over-committed, so you're asking a question about the tasks manager in your OS, not about the tasks themselves. In general, however, that's not a very big part of your answer.

Now suppose that the tasks are NOT independent. The time that those tasks spend coordinating with each other MIGHT be different when comparing 4 tasks to 5 tasks, but the biggest loss is how much time tasks must wait before they can actually coordinate with each other. To take a completely absurd example, suppose you have many tasks which need one second of processing time before they have to coordinate plus one more task which must run for 100 seconds before it's ready to exchange coordination information. All of the one second jobs can be completed and simply waiting for the 100 second job to finish. The number of workers is unimportant because so much time is spent waiting for that one long process to finish. (The average CPU utilization would be dismally low, too.)

From that absurd example, you can see that a very important part of the answer depends on whether your 4 or 5 tasks are relatively equal in processing requirements or relatively unequal. There is no general answer to whether a job can be divided into 4 equal pieces or 5 equal pieces or if some other number would be more efficient, and from our perspective (outside of SMP) there's no way for us to tell.

Fair enough, just wondering if anyone even tried such a scenario.

Thanks

next gen cpu from intel and amd have a new parallelization architecture. this introduces a 256 bit SIMD capability with the addition of a few new assembly instructions. It is assumed that this target will be supported through OpenCL. It would be interesting to fully utilize your CPU's parallel capabilities at the same time keeping a supplmental GPU with its own massive capabilities running at the same time. we'll have to see how this will affect AMD's motivation to improve on existing GPU design, and how NVIDIA will react.


A brief overview:
http://en.wikipedia.org/wiki/Advanced_Vector_Extensions


edit: ok maybe I don't quite understand SIMD as well as I thought I did.

well technically it wont, just because what GPU stands for. lets break it down, graphics processing unit, only difference between cpu and gpu is location and dedication and era of processor, cause if any graphics company that also makes there own cpu's, would easily throw out the its not fair card of lets put a reduced speed muit-core gpu (which currently doesnt exist, only higher speeds for servers for specail needs funny thing is though gpu's are WAY more than the avgerage house needs)

Just thought I'd resurrect this thread to give a report on the difference between Core 2 and i7...

I replaced my Q9450 rig with an i7-3770S Ivy Bridge. Without overclocking, the new machine folds AT LEAST 3X the PPD as the old one! My Q9650+Q9450 used to fold around 15K PPD. Now the Q9650+3770S fold around 45K PPD!

While the boost from 2.66 to 3.1 GHz accounts for some of the boost, the hyperthreading and overall architecture of the Ivy bridge must account for the bulk of the increase in Folding prowess. The bonus is a reduction of power consumption by 29 Watts (from 95 to 66 W TDP), though HWMonitor reports package power at <50 W while Folding...

After installing a new PSU in my older machine, I was measuring power consumption (at the UPS) of each of my rigs. The Q9650 is on a P35 MoBo, and the i7-3770S is on a Z77. The Vcore for the Q9650 is set at 1.150; VID is 1.156. The i7 is at default. Both have 8 GB RAM and Fold SMP. While the i7 system uses significantly less power overall, it appears they both increase by 54 Watts from idle to Folding.

That was a surprise to me, because I would expect the Q9650 with a TDP of 95W would increase more than the i7 with a TDP of 66W. HWMonitor confirms that the power attributed to the "cores" on the i7 is under 4W at idle and 42-43W while Folding; there is no similar function available on the P35 system.

Can anyone tell me if there is a relationship between rated TDP and actual expected CPU power burn? It seems I'm using significantly less than TDP at 100% CPU load...

http://en.wikipedia.org/wiki/Thermal_design_power 2nd sentence...

I wonder when chip manufacturers reclassified gromacs as a "real application" rather than as a "power virus."

jrweiss wrote:After installing a new PSU in my older machine, I was measuring power consumption (at the UPS) of each of my rigs. The Q9650 is on a P35 MoBo, and the i7-3770S is on a Z77. The Vcore for the Q9650 is set at 1.150; VID is 1.156. The i7 is at default. Both have 8 GB RAM and Fold SMP. While the i7 system uses significantly less power overall, it appears they both increase by 54 Watts from idle to Folding.

That was a surprise to me, because I would expect the Q9650 with a TDP of 95W would increase more than the i7 with a TDP of 66W. HWMonitor confirms that the power attributed to the "cores" on the i7 is under 4W at idle and 42-43W while Folding; there is no similar function available on the P35 system.

Can anyone tell me if there is a relationship between rated TDP and actual expected CPU power burn? It seems I'm using significantly less than TDP at 100% CPU load...

I guess there is an error in determining the VID voltage. I have Q9650/3.0 GHz, VID: 1.262V. Now is @3.5 GHz/1,225 V in BIOS (mobo without LLC ). CPU-Z - 1.155V under 100% load, client v6.34. Vcore under load reduced by ~ 0,060-0,070V, if there is no LLC. Lower voltage indicates a lower consumption (power).
Currently Q9650 worked with box cooler (from C2D E6400/65 W), 65-72*C; ambient - 22-25*C. Perhaps chip on these processors has a high quality.

VID on the Core2 CPUs varied by individual CPU, and was stamped on the case IIRC. Max was 1.3625, default in BIOS was 1.2625, and many had VID ratings significantly under that. It is important to note that any OC overvoltage should be based on individual VID, not on the "standard" Vcore. Heat production will increase with both clock speed and voltage.

Voltage readings in CPUz and other utilities usually reads a bit lower than is set in BIOS due to normal resistance and voltage losses in the circuits.

I set up a sandy bridge i3 for a client last week. The i3 has 2 cores with 4 threads, (hyperthreading) I used SMP:2 as I expected much of the time to be spent doing SIMD instructions. Has anyone done tests of the i3 or i7 (as I understand it, the i5 does not hyperthread) trying SMP:number of threads vs SMP:number of cores? It is not a dedicated folder, if that is important.

2 core i5's do have HT, the 4 core models do not. I don't know of any specific tests on the i3, but tests done in the past that I read on i7's showed 10-20% increases in folding throughput from HT threads being used compared to just the base core count. Those reports were consistent with what I saw on my i7 comparing SMP:6 to SMP:8.