Folding Forum

If I read it correctly, you'll get full speed from BD without a recompile of FAH, but only half speed from SB until FAH is recompiled with AVX. I see what you are saying. AMD's method will allow legacy code to use all of the 256-bit FPU whereas Intel's method requires AVX in order to split the FPU ...

It might not affect anything at all. Last I knew they were switching the core over to OpenCL which Nvidia has separate drivers for. Then again their implementation of OpenCL could just plug into CUDA in the background or simply be CUDA with the OpenCL API on the front side.

Added the link. The other consideration is how many operations can be done simultaneously. Some AMD fanboys have criticized the Intel fanboys because chips like the i7 have virtual cores rather than real cores and imply that Bulldozer will have real cores. Well from what I can tell Bulldozer will be...

I came across an article outlining the floating point processing unit in the upcoming AMD Bulldozer processor. Since 90% of my CPU usage goes to F@H, this paragraph caught my attention. The floating point unit is also much more robust than it used to be. The Phenom had a single 128 bit unit per core...